With the development of very deep sub-micron (VDSM) technology, semiconductor design and processing techniques may require increasing complexity. In addition, on-chip variations may occur, for example, due to changes in power supply voltage and/or temperature. For instance, semiconductor device characteristics measured using a Test Element Group (TEG) in a scribe lane may not properly reflect the characteristics of the actual devices that may be present in a chip. As such, it may be difficult to set timing margins that may be suitable for proper device operation.
More particularly, in circuits manufactured using very deep sub-micron technology, the clock frequency may be increased to the GHz range in order to achieve higher performance. Therefore, the period of the clock signal may be decreased below the nanosecond range. However, in a single circuit, the clock signal may control data flow under timing constraints from thousands of registers. To satisfy these timing constraints, it may be necessary to control the timing of the delay of the signals that reach each register, as the timing constraints may be violated when the signal delay is different from a target value. Such a violation of the timing constraints may cause an erroneous system operation. Accordingly, it may be desirable to measure the propagation delay and timing margin of signals in the system.
However, according to conventional methods of measuring on-chip delay and/or setup/hold timing margin in a semiconductor device, a test chip and/or a special logic, such as a digital locked loop (DLL) may be used. As such, the actual data path of a synchronous circuit may not be reflected. As a result, it may be difficult to design an application-specific integrated circuit (ASIC) and/or a system on-chip (SOC) using conventional methods.